Figure 80. IBM System/7
The 1130 system can provide expanded facilities to the IBM System/7 (a sensor based system described in IBM System/7 System Summary, Order No. GA34-0002). To the 1130, the sensor based system (Figure 80) appears to be another I/O unit attached to the storage access channel (SAC or SAC II). Communication between the System/7 and the 1130 is by means of 1130-initiated storage-to-storage data transfers with a mutual interrupt system. The mutual interrupt system allows either system to signal the other that a transfer of data is either desired or completed. Facilities are provided to alert the 1130 in case of interface error or System/7 malfunction and to enable the 1130 to determine the nature of the error or malfunction.
Figure 80. IBM System/7
Standard 1130 execute I/O instructions are used to control the System/7. XIO control instructions are used to transmit the beginning System/7 storage address and the word count of the number of words to be transmitted. (See "Storage Access Channel.") An XIO initiate read or initiate write instruction is used to transfer data between the 1130 core storage and the System/7 main storage. An XIO sense interrupt instruction is used to identify that the System/7 has interrupted the 1130. The System/7 interrupts on interrupt level 3, interrupt level status word bit 4. An XIO sense device instruction is used to obtain status indications from the System/7. For details of the instruction formats and programming considerations, refer to IBM System/7 Functional Characteristics, Order No. GA34-0003.
The IOCC specifies the operation to be performed and the device to which the operation is directed. For data transfer operations, the IOCC also specifies the word count or address of the data to be transferred.
An IOCC must start at an even storage address in the 1131 processor and has the following format:
The IOCC fields are described as follows:
Word Count Address: This field is used to pass the three values required by the System/7 1130 host attachment in order to perform a data transmission: (1) a transmission word count, (2) a System/7 storage address, and (3) an 1130 storage address. The count specifies the number of data words to be transferred. The addresses establish the beginning of the data tables between which the data transfer is to occur. The count and one of the addresses are transferred to System/7 storage by two separate control IOCC's. The third value, an address, is transferred by the 1130 initiate read or initiate write IOCC.
Device: This 5-bit field identifies the I/O device to which the IOCC is directed. In this case, a binary 01100 is the code identifying the System/7.
Function (Fun): The 3-bit function code determines the specific I/O operation to be performed.
Modifier: This 8-bit field provides additional information, when necessary, for the function specified.
Control (100)
An XIO instruction with a control IOCC loads the System/7 1130 host attachment with one of two parameters necessary before starting a data transfer operation between the System/7 and the 1130. The two parameters are:
The 1130 storage address involved in the data transfer is indicated subsequently in either the 1130 initiate read or initiate write IOCC.
Since only one of the two parameters can appear in a single control IOCC, two control IOCC's are required (and, hence, two XIO instructions) prior to performing the actual data transfer.
Modifier bits 14 and 15 signal which, if either, of the two parameters is contained in the control IOCC as follows:
Modifier bits 12 and 13 of the control IOCC determine the basic interruption controls to be established in the attachment. To establish the basic control status, modifier field bits 12 and 13 are set as follows:
Modifier field bit 14 serves a dual purpose in a control IOCC. This bit also establishes a temporary interruption control status as follows:
The temporary control status is temporary only in the sense that an initiate read command, an initiate write command, or another control command, immediately following such a control IOCC, can return the interruption control status to the basic control status.
Initiate Read (110)
An XIO instruction with an initiate read IOCC sends a block of contiguous data from System/7 to 1130 storage. The starting location of the System/7 data and the number of words transferred must have been established by previously executed control IOCC's. The address field of the initiate read IOCC contains the starting location in 1130 storage for the data to be received.
Modifier field bit 15 is used to control interruptions as follows (refer also to "Interruptions to System/7"):
Initiate Write (101)
An XIO instruction with an initiate write IOCC sends a block of contiguous data from 1130 storage to System/7 storage. The number of words transferred and the System/7 starting location into which they are stored must have been established by previously executed control IOCC's. The address field of the initiate write IOCC contains the starting location in 1130 storage for the data to be transmitted.
Modifier field bit 15 is used to control interruptions as follows (refer also to "Interruptions to System/7"):
Electronic Initial Program Load (101)
An XIO instruction with this special initiate-write IOCC is used to IPL the System/7 from the 1130. Modifier bit 14 in this IOCC serves a dual purpose for the electronic initial program load (EIPL) function. This bit also establishes a temporary "prevent" status for attention and power/thermal interruptions. Thus, the 1130 will not recognize an attention or power/thermal warning interruption during a EIPL to the System/7. The basic interruption status must be reestablished by a control command with modifier field bit 14 = 0 or by an initiate read or initiate write command.
The host attachment switch on the System/7 console must be in the enable and IPL position for this command to perform the IPL. When the 1130 host attachment recognizes the EIPL command, the System/7 does a system reset and enters the wait state. The host attachment sets the System/7 address to 0 and proceeds with the EIPL as if it were a normal initiate-write from the 1130.
For an error-free termination, the System/7 instruction address register is set to a 0 value, priority level 3 is activated, and System/7 begins to execute instructions starting at location 0. A standard operation-end interrupt is also generated in the 1130.
For an error termination, the System/7 is not informed of the IPL termination, a standard operation-end interrupt is generated in the 1130, and the error condition is indicated by setting a corresponding status bit in the DSW for the 1130.
A word count must be established in the 1130 host attachment prior to attempting an EIPL operation from the 1130. This word count is established by an XIO instruction with a control IOCC.
A System/7 address need not be established, since the host attachment sets this address to 0.
The program in the 1130 can request an interruption to the System/7 processor module. The interrupt priority level, sublevel, and device address are fixed for the 1130 host attachment. As directed by a bit in an initiate read or initiate write IOCC, the request to the System/7 processor is made on priority level 3 with a sublevel of 0. The interruption request presented to the System/7 by the 1130 is handled the same as any other priority interruption request.
An XIO instruction with a sense interrupt IOCC loads the 1130 accumulator with the interrupt level status word (ILSW) associated with the highest priority level that is on, in order to determine the interrupting device. The sense interrupt command is common to all 1130 I/O devices; therefore, no device-code field is needed.
A System/7 interrupt request to the 1130 sets on ILSW bit 4 for interruption level 3. (The System/7 and the IBM 2250 Display Unit are mutually exclusive on the 1130 SAC.)
An XIO instruction with a sense device IOCC loads the 1130 accumulator with the DSW from the 1130 host attachment in the System/7. The 1130 can determine the cause of an interruption by analyzing these DSW bits.
Modifier field bit 15 has the following meaning in this IOCC:
DSW bits can also be reset by turning on System/7 power or by the reset line in the 1130 SAC.
Figure 81. System/7 Device Status Word
Device Status Word (DSW}: The 16-bit device status word associated with the 1130 host attachment has various bits set on to indicate program operating status and detected errors.
The significant bits in the DSW presented to the 1130 processor and their meanings are:
| Significant Bits | Meaning | |
| 0 | Attention. A System/7 set interrupt command is directed to the 1130. This is not an error. | |
| 1 | Operation end. The word count equals zero, or a power/thermal warning or error was detected during a data transfer operation. | |
| 2 | Invalid storage address. The 1130 has attempted to address a storage location outside the installed capacity of the System/7. This is an error. | |
| 3 | Data check. A System/7 parity error was detected by the 1130 host attachment when fetching words from System/7 storage. This is an error. | |
| 4 | Count = 0. The word count register in the 1130 host attachment is equal to 0. This is not an error. | |
| 5 | Power or thermal warning. A power failure or thermal warning condition has occurred. This bit is not reset by the sense-device IOCC. | |
| 6 | Storage control check. The 1130 host attachment detected that System/7 storage has not responded to the attachment's request for a storage cycle, sometimes referred to as an "overrun" condition. This is an error. | |
| 14 | Ready. The System/7 is on line and power is good. This bit is not reset by the sense-device IOCC. This is not an error. | |
| 15 | Busy. The 1130 host attachment is performing a data transfer operation between the attachment and System/7 storage. This bit is turned off as soon as the operation-end bit (bit 1) is set on. Any 1130 command (except sense-device) to the 1130 host attachment is ignored if the busy bit is on. This is not an error. |
The System/7 1130 host attachment presents interruptions to the 1130 on its interruption level 3. Interruption requests are made to the 1130 under any of the following conditions:
The interruption that occurs at the operation-end time of a data transfer can be directed to the System/7 as well as to the 1130. However, if an error is detected during the data transfer, the operation is terminated and the interruption is directed to the 1130 only (count = 0 DSW bit may or may not be set on).
When the System/7 directs a set interrupt command to the 1130 attachment, the DSW attention bit (bit 0) is set on unless it is already on. If already on, condition code 2 is returned to the System/7. If the 1130 attachment is busy, the attention bit is set on and indicated to the 1130 at the time an operation-end interrupt occurs for the operation in progress. If the 1130 attachment is not busy, the attention bit is set on and an interruption request is made to the 1130 on its priority level 3 unless attention interruptions are inhibited by the host attachment interruption controls.
The host attachment interruption controls, which permit or prevent attention and power/thermal interruptions to the 1130, are determined by the setting of modifier field bits 12 to 14 in an 1130 IOCC. Modifier bits 12 and 13 are the basic interruption control; bit 14 is a temporary interruption control. Attention and power/thermal interruptions are permitted only if the basic status is "permit" and there is no temporary "prevent." If the basic status prevents attention and power/thermal interruptions, these interruptions are not permitted again until another control IOCC that alters the basic interruption control status is executed to permit the interruptions.
If interruptions are temporarily prevented as directed by bit 14 in a control IOCC, they are not permitted again until one of the following occurs:
Following any of these events, the 1130 host attachment returns to the basic interruption control status.
Attention and power/thermal interruptions to the 1130 are also prevented by either a System/7 power-on reset or an 1130 storage access channel reset. These interruptions are not permitted again until a control IOCC is executed to establish a basic interruption control status.
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