The storage access channel (SAC) provides the 1130 with additional I/O capability. If the 1403 Printer, 2311 disk storage, or 2310 Disk Storage is included in the system, it is necessary to attach the 1133 Multiplex Control Enclosure to the SAC. However, an additional channel (SAC II) is provided by the 1133 as a special feature.
Through the facilities of SAC or SAC II, the user may attach his own device or the IBM 2250 Display Unit. The customer device may interrupt on any level from 2 through 5. Any bit within ILSW's 2 through 5 that has not been previously assigned may be used. This is also true for the assignment of area codes for the customer device. The customer device may be assigned any area code that has not been previously assigned.
The storage access channel feature allows external devices or systems to communicate directly with the 1131 core storage unit. The transfer of data to or from core storage and the SAC takes place in one of two modes.
Because of the SAC's ability to interrupt on levels 2, 3, and 5, interrupt level status words for these levels, as well as for level 4, are provided so that the CPU program may determine which device caused the interrupt.
When an interrupt is caused by a basic device, the CPU program must give an XIO sense interrupt command. The attachment for the device places the ILSW bit for that device on the I/O input bus, and reads the bit into the B-register and transfers to the accumulator. If a device on the SAC causes an interrupt, the CPU program must give an XIO sense interrupt command, and the device must decode the command and place its ILSW bit on the I/O input bus to be read into the B-register.
When an XIO sense device command is given to the SAC, the device must decode the command and set the status bits on the I/O input bus.
The customer must provide his own interrupt routines and controlling programs.
The customer may assign to devices on the SAC any area codes that are not already assigned to a basic device on his system. The decoding of the area codes is done in the devices on the channel.
The customer may assign any bit in the ILSW to a device on the SAC that is not assigned to a basic device on his system.
No change is made to the 1131 or the SAC attachment in the assignment of area codes, interrupt levels or ILSW bits.
There are four cycle-steal priority levels. The CPU Disk Storage is on level 0; SAC is on level 1; the 1132 is on level 2; and the 2501 is on level 3. There is no polling of cycle steal requests. That means the SAC, by keeping its request active, may completely block the 1132 printer and other lower priority devices.
The storage access channel (SAC) operates on the IBM 1130 system under direct program control or cycle-steal control.
An XIO instruction addresses an I/O control command (IOCC) word, which is placed on the I/O output bus.
The devices or systems on the SAC must decode the IOCC area code to select one device or system for the operation.
The device or system selected must decode the function field and control the transfer of data to or from core storage.
Sense Interrupt (011)
The sense interrupt IOCC is placed on the I/O output bus, and the interrupt level being serviced is sent to SAC. The device then sets its assigned bit on the I/O input bus. The CPU program then analyzes the ILSW and branches to the subroutine for the device.
The customer assigns interrupt status bits for the devices on the channel in his programs. The devices may being up an interrupt status bit assigned by the customer. [preceding is correct, if unclear] The interrupt status bits may be any bits not used by a basic device.
Sense Device (111)
This command sets the IOCC on the I/O output bus. The devices decode the area code and the selected device decodes the sense device function and sets the device status word (DSW) bits on the I/O input bus to read into the accumulator.
The conditions causing the interrupt are turned off by setting the modifier bit 15 to 1. If the device interrupts on more than one level, the conditions are turned off by modifier bit 15 for the highest level, bit 14 for the next highest level, etc.
Control (100)
This command sets the IOCC on the I/O output bus. The devices decode the area code. The selected device decodes the control function and sets controls in the device to perform the action specified by the modifier bits (8-15) of EA + 1 or EA (address word). The device and the customer - provided programs control the function to be performed.
Read (010)
This command sets the IOCC on the I/O output bus. The devices decode the area code. The selected device decodes the read function and sets a single word on the I/O input bus.
Write (001)
This command sets the IOCC on the I/O output bus. The devices decode the area code. The selected device decodes the write function and takes the word from the I/O output bus.
Initiate Read (110)
This command sets the IOCC on the I/O output bus. The devices decode the area code. The selected device decodes the initiate read function and sets the controls in the device for cycle-steal operation.
The word count address (WCA) is sent to the device. The first cycle-steal cycle is taken and the word count is transferred to the device. The device then controls the transfer of data to the CPU core storage by cycle-steal level 1 cycles until the number of words specified by the word count has been transferred.
Initiate Write (101)
This command sets the IOCC on the I/O output bus. The devices decode the area code. The selected device decodes the initiate write function and sets the controls in the device for cycle-steal operation.
The word count address (WCA) is sent to the device. The first cycle-steal cycle is taken and the word count is transferred to the device. The device then controls the transfer of data from the CPU core storage to the device by cycle-steal level 1 cycles until the number of words specified by the word count has been transferred.
For additional information regarding SAC, refer to IBM 1130/1133/SAC, Original Equipment Manufacturers' Information, Order No. GA26-3645.
Since no power sequencing is provided by the CPU, one of the following procedures must be followed when powering up or down of the I/O device attached to the SAC to avoid possible loss of data:
But wait, there's MORE...
And there's LESS...
And there's the rest