Mnemonic
STO |
Description
The contents of the accumulator replace the contents of the addressed core-storage location. Contents of the accumulator are unchanged by the operation.
There are no addressing exceptions for the load accumulator instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the STO instruction.
Indicators: The carry and overflow indicators are not affected during the STO operation.
Examples
Store Accumulator
Assembler Language Coding | Hexadecimal Value | Description of Instruction | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Label | Operation | F | T | ||||||||
|
|
32 | 33 | 35..40.. | |||||||
STO | DISP | D0XX | Contents of A are stored in CSL at EA (I + DISP) | ||||||||
STO | 1 | DISP | D1XX | Contents of A are stored in CSL at EA (XR1 + DISP) | |||||||
STO | 2 | DISP | D2XX | Contents of A are stored in CSL at EA (XR2 + DISP) | |||||||
STO | 3 | DISP | D3XX | Contents of A are stored in CSL at EA (XR3 + DISP) | |||||||
STO | L | ADDR | D400XXXX | Contents of A are stored in CSL at EA (Addr) | |||||||
STO | L | 1 | ADDR | D500XXXX | Contents of A are stored in CSL at EA (Addr + XR1) | ||||||
STO | L | 2 | ADDR | D600XXXX | Contents of A are stored in CSL at EA (Addr + XR2) | ||||||
STO | L | 3 | ADDR | D700XXXX | Contents of A are stored in CSL at EA (addr + XR3) | ||||||
STO | I | ADDR | D480XXXX | Contents of A are stored in CSL at EA (V in CSL at Addr) | |||||||
STO | I | 1 | ADDR | D580XXXX | Contents of A are stored in CSL at EA (V in CSL at "Addr + XR1") | ||||||
STO | I | 2 | ADDR | D680XXXX | Contents of A are stored in CSL at EA (V in CSL at "Addr + XR2") | ||||||
STO | I | 3 | ADDR | D780XXXX | Contents of A are stored in CSL at EA (V in CSL at "Addr + XR3") |
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