Store Double
Organizational graphic tag to help group instructions

Mnemonic

 STD

Short and Long format of instruction



Description

The contents of the accumulator and its extension are loaded into two consecutive words in core storage. These two consecutive words in core storage are located by the effective address as follows:

  1. The first word is at the location specified by the effective address generated during instruction execution. The effective address should specify an even-word location.
  2. The second word is at the word location immediately following the location specified by the effective address.
Before and after operation illustration

Contents of the accumulator and its extension remain undisturbed as a result of the operation.

Note: If an odd-word location is addressed first, the contents of the accumulator are stored into that location, and the contents of the accumulator extension are not stored. In normal operation, then, the effective address generated as a result of execution of the STD instruction should point to an even-word location in core storage. If only the accumulator contents are to be stored into a core storage word, then the STO instruction should be used.

There are no addressing exceptions for the STD instruction; all forms of addressing described under "Effective Address Generation" apply to the STD instruction.


Indicators: The carry and overflow indicators are not affected during execution of an STD instruction.



Examples


Store Double

Assembler Language Coding Hexadecimal Value Description of Instruction
Label   Operation   F T    
21 25
  
27 30
   32 33   35..40..
    STD         DISP D8XX Contents of A and Q are stored in CSL at EA (I + DISP) and EA+1
    STD     1   DISP D9XX Contents of A and Q are stored in CSL at EA (XR1 + DISP) and EA+1
    STD     2   DISP DAXX Contents of A and Q are stored in CSL at EA (XR2 + DISP) and EA+1
    STD     3   DISP DBXX Contents of A and Q are stored in CSL at EA (XR3 + DISP) and EA+1
    STD   L     ADDR DC00XXXX Contents of A and Q are stored in CSL at EA (Addr) and EA+1
    STD   L 1   ADDR DD00XXXX Contents of A and Q are stored in CSL at EA (Addr + XR1) and EA+1
    STD   L 2   ADDR DE00XXXX Contents of A and Q are stored in CSL at EA (Addr + XR2) and EA+1
    STD   L 3   ADDR DF00XXXX Contents of A and Q are stored in CSL at EA (addr + XR3) and EA+1
    STD   I     ADDR DC80XXXX Contents of A and Q are stored in CSL at EA (V in CSL at Addr) and EA+1
    STD   I 1   ADDR DD80XXXX Contents of A and Q are stored in CSL at EA (V in CSL at "Addr+XR1") and EA+1
    STD   I 2   ADDR DE80XXXX Contents of A and Q are stored in CSL at EA (V in CSL at "Addr+XR2") and EA+1
    STD   I 3   ADDR DF80XXXX Contents of A and Q are stored in CSL at EA (V in CSL at "Addr+XR3") and EA+1

But wait, there's MORE...

Valid HTML 4.01 Transitional