Load Double
Organizational graphic tag to help group instructions

Mnemonic

 LDD

Short and Long format of instruction



Description

The accumulator and accumulator extension are loaded with two consecutive words from core storage. The two consecutive words in core storage are located by the effective address as follows:

  1. The first word is at the location specified by the effective address generated during instruction execution. The effective address should specify an even-word location.
  2. The second word is at the word location immediately following the location specified by the effective address.
Before and after operation illustration

Contents of the two core storage words remain undisturbed as a result of the operation. The accumulator and extension can contain any value before the LDD instruction is executed; however, the value of the two core storage words appears in the accumulator and its extension at the end of the operation.

Note: If an odd-word location is addressed first, then the contents of that location are loaded into both the accumulator and its extension. For example, if an odd-word location contains DFEA (hexadecimal), and that word is addressed first during execution of an LDD instruction, the DFEA appears in both the accumulator and its extension. In normal operation, then, the effective address generated as a result of execution of the LDD instruction should point to an even word location in core storage.

There are no addressing exceptions for the LDD instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the LDD instruction.


Indicators: The carry and overflow indicators are not affected during an LDD operation.



Examples



Load Double

Assembler Language Coding Hexadecimal Value Description of Instruction
Label   Operation   F T    
21 25
 
27 30
  32 33   35..40..
    LDD         DISP C8XX Contents of CSL at EA (I + DISP) and EA + 1 are loaded into A and Q
    LDD     1   DISP C9XX Contents of CSL at EA (XR1 + DISP) and EA + 1 are loaded into A and Q
    LDD     2   DISP CAXX Contents of CSL at EA (XR2 + DISP) and EA + 1 are loaded into A and Q
    LDD     3   DISP CBXX Contents of CSL at EA (XR3 + DISP) and EA + 1 are loaded into A and Q
    LDD   L     ADDR CC00XXXX Contents of CSL at EA (Addr) and EA + 1 are loaded into A and Q
    LDD   L 1   ADDR CD00XXXX Contents of CSL at EA (Addr + XR1) and EA + 1 are loadedinto A and Q
    LDD   L 2   ADDR CE00XXXX Contents of CSL at EA (Addr + XR2) and EA + 1 are loaded into A and Q
    LDD   L 3   ADDR CF00XXXX Contents of CSL at EA (addr + XR3) and EA + 1 are loaded into A and Q
    LDD   I     ADDR CC80XXXX Contents of CSL at EA (V in CSL at Addr) and EA + 1 are loaded into A and Q
    LDD   I 1   ADDR CD80XXXX Contents of CSL at EA (V in CSL at "Addr + XR1") and EA+1 are loaded into A and Q
    LDD   I 2   ADDR CE80XXXX Contents of CSL at EA (V in CSL at "Addr + XR2") and EA+1 are loaded into A and Q
    LDD   I 3   ADDR CF80XXXX Contents of CSL at EA (V in CSL at "Addr + XR3") and EA+1 are loaded into A and Q


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