Mnemonic

Description

The purpose of this instruction is to shift the contents of the accumulator left, a bit at a time, as in the shift-left-accumulator instruction. Zeros are shifted into position 15 of the accumulator and then to the left in order to fill vacated positions. Execution of the shift-left-and-count-accumulator instruction stops when:

1. A 1-bit value is in bit-position 0 of the accumulator, or
2. The shift count is decremented to zero.

The location of the shift count is specified by the T bits of the instruction as follows:

Note: When the T bits are 00, the shift-left-and-count-accumulator instruction is executed in exactly the same manner as a shift-left-accumulator instruction (SLA) with its T bits set to 00.

When execution of a shift-left-and-count-accumulator instruction starts, the shift count is automatically moved from the specified index register to CPU circuits that do the counting. When the operation is ended, the specified index register is updated as follows:

If the count is decremented to zero before a 1 is shifted into accumulator-bit 0, the residual count is zero. If a 1 is shifted into accumulator-bit 0 before the count is decremented to 0, the operation is ended. In this latter case, the remaining count value is loaded back into the index register. For example:

In this example, the initial count is 3, but after one shift has occurred, a 1 is in accumulator bit-position 0. This 1 ends the operation. One shift has occurred, so the residual count stored into the index register is 2 (3 - 1 = 2).

If the shift count is initially zero, the instruction performs as a no-operation, regardless of the value of accumulator-bit 0. In this case, no shifting occurs, the carry indicator is not changed, and none of the bits in the specified index register are altered.

If accumulator-bit 0 is initially at a value of 1 and the initial count does not equal zero, the carry indicator is turned on. Also, bits 8 and 9 of the specified index register are reset to 00, but the count is not changed. Again, shifting does not occur.

Core storage is not addressed during execution of a shift-left-and-count-accumulator instruction.

Programming Note: This instruction is particularly useful in determining specific device status and interrupt conditions. After a device status word or interrupt-level status word has been loaded into the accumulator, a shift-left-and-count-accumulator instruction can be executed so that the first 1 into accumulator position 0 stops the operation. The residual count, stored back into the specified index register, can then be used to index to the desired sub-routine. A unique subroutine is then specified for each bit in the accumulator and is indexed by the residual count. Refer to "I/O Interrupts" for a general description of the device status words and the interrupt-level status words. Specific device-status-word bit definitions are in each I/O device description.

Indicators: The carry indicator is set or reset differently for the shift-left-and-count-accumulator instruction than it is for the shift-left-accumulator instruction. The carry indicator can have the following values after execution of a shift-left-and-count-accumulator instruction:

Count	Accumulator Bit 0 Equals		Carry Indicator Equals
0	1		1
= 0	1		0
= 0	0		0

The carry indicator is set or reset by bits shifted out of accumu1ator-bit 0 in the shift-left-accumulator instruction but not in the shift-left-and-count-accumulator operation. In the shift-left-and-count-accumulator operation, the carry indicator is affected as shown in the immediately preceding table.

If, however, the T bits (in a shift-left-and-count instruction) are 00, the carry indicator is affected exactly as described in the shift-left-accumulator instruction description.

The overflow indicator is not affected by the shift-left-and-count-accumulator operation.

Examples

Shift Left and Count Accumulator

For the four examples below, assume that the index register was previously loaded by an LDX instruction. Only the low-order bit positions (10-15) of the index register (XR) are shown, and only the high-order bit positions (0-5) of the accumulator (A) are shown. Those bit positions containing an X can be 0 or 1.

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