Add Double
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Mnemonic

 AD

Short and Long format of instruction



Description

The purpose of this instruction is to add two 32-bit operands. One of the operands must be loaded into the accumulator and accumulator extension before the add-double operation is performed. A load-double instruction can be used to do this.


Illustration of ADD DOUBLE instruction memory states

The add-double instruction addresses another operand in core storage; this operand must also be at an even-word address, just as the leftmost word addressed by the load-double instruction.

Except for the size of the operands, the add-double operation proceeds in much the same manner as the add operation:


  1. The result of the add-double operation is placed in the accumulator and accumulator extension.
  2. Result of the addition is either positive or negative: + plus a + = + - plus a - = - + plus a - = sign of the larger operand - plus a + = sign of the larger operand
  3. The value in the accumulator and accumulator extension has a sign as signified by bit 0 in the accumulator. The leftmost bit of each operand determines that operand's sign.
  4. The operand in core storage is unchanged by the operation. Pictorially, the operation proceeds as follows:
Operation of Add Double

If the add-double instruction addresses an operand starting at an odd address, the contents of that single word are added to both the accumulator and to the accumulator extension.

There are no other addressing exceptions for the add-double instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the AD instruction.


Indicators: The carry indicator is automatically reset to 0 at the beginning of execution of an add-double instruction. If, during the add-double execution, a carry occurs out of the leftmost position of the accumulator, then the carry indicator is set to 1; if no such carry-out occurs, the carry indicator remains reset. It can subsequently be set or reset by the various actions listed under "Carry and Overflow Indicators" (see Figure 13).

The overflow indicator must be reset to 0 if it is to be used during execution of an add-double instruction. If the overflow indicator is at a value of 1 at the start of an add-double operation, it is not changed regardless of the result of the operation.

If the overflow indicator is at a value of zero at the start of an add-double operation, it is set to a value of 1 if the addition produces a result that exceeds the capacity of the accumulator plus the accumulator extension. For example, assume that the following two negative numbers are added together:


 1 000 0000 0000 0000 0000 0000 0000 0000
+1 000 0000 0000 0000 0000 0000 0000 0000
C0 000 0000 0000 0000 0000 0000 0000 0000

(S = sign bit; C = carry out of high-order position.)

This result is greater than the capacity of the accumulator plus accumulator extension because adding the two largest negative numbers should not yield a positive zero, which is the result in the accumulator plus its extension. In this case, the overflow indicator is set to 1. The carry indicator would also be set to 1 because of the carry-out of the leftmost position of the accumulator. Refer to "Carry and Overflow Indicators" for a discussion of how these two indicators can be used together in certain arithmetic operations.

Maximum capacity of the accumulator and accumulator extension is:

Power-of-2 Notation Decimal Notation Hexadecimal Notation
+231-1 +2,147,483,647 +7FFFFFFF
-231 -2,147,483,648 -80000000

Examples

Add Double

Assembler Language Coding Hexadecimal Value Description of Instruction
Label   Operation   F T    
21 25
 
27 30
  32 33   35..40..
    AD         DISP 88XX Add contents of CSL at EA (I+DISP) and EA+1 to A and Q
    AD     1   DISP 89XX Add contents of CSL at EA (XR1+DISP) and EA+1 to A and Q
    AD     2   DISP 8AXX Add contents of CSL at EA (XR2+DISP) and EA+1 to A and Q
    AD     3   DISP 8BXX Add contents of CSL at EA (XR3+DISP) and EA+1 to A and Q
    AD   L     ADDR 8C00XXXX Add contents of CSL at EA (Addr) and EA+1 to A and Q
    AD   L 1   ADDR 8D00XXXX Add contents of CSL at EA (Addr+XR1) and EA+1 to A and Q
    AD   L 2   ADDR 8E00XXXX Add contents of CSL at EA (Addr+XR2) and EA+1 to A and Q
    AD   L 3   ADDR 8F00XXXX Add contents of CSL at EA (Addr+XR3) and EA+1 to A and Q
    AD   I     ADDR 8C80XXXX Add contents of CSL at EA (V in CSL at Addr) and EA+1 to A and Q
    AD   I 1   ADDR 8D80XXXX Add contents of CSL at EA (V in CSL at "Addr+XR1") and EA+1 to A and Q
    AD   I 2   ADDR 8E80XXXX Add contents of CSL at EA (V in CSL at "Addr+XR2") and EA+1 to A and Q
    AD   I 3   ADDR 8F80XXXX Add contents of CSL at EA (V in CSL at "Addr+XR3") and EA+1 to A and Q


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