Mnemonic
| STX |
Description
Contents of the specified register are stored in the addressed core-storage location. The T bits, in the short or the long format, specify the register.
| T bits | Register | |
|---|---|---|
| 00 | Instruction address | |
| 01 | Index-register 1 | |
| 10 | Index-register 2 | |
| 11 | Index-register 3 |
The contents of the register remain unchanged as a result of the operation.
For the short-instruction format, the addressed core-storage location is always specified by adding the displacement to the contents of the instruction-address register. The contents of XR1, XR2, and XR3 are never used to form the effective address in an STX operation.
Pictorially, a short-format STX operation can be shown as follows:
For the long-instruction format, addressing is either direct or indirect in the normal manner. However, as in the short format of this same instruction, the index registers are not used to form the effective address. Also, as is the case with other long-format instructions, the instruction-address register is not used in the long format to form the effective address. The value in the instruction-address register can, nevertheless, be stored in the specified storage location.
A long-format STX operation with indirect addressing can be represented pictorially as follows:
Indicators: The carry and overflow indicators are not affected during execution of an STX instruction.
Examples
Store Index
| Assembler Language Coding | Hexadecimal Value | Description of Instruction | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Label | Operation | F | T | ||||||||
|
|
32 | 33 | 35..40.. | |||||||
| STX | DISP | 68XX | Store I in CSL at EA (I+DISP) | ||||||||
| STX | 1 | DISP | 69XX | Store XR1 in CSL at EA (I+DISP) | |||||||
| STX | 2 | DISP | 6AXX | Store XR2 in CSL at EA (I+DISP) | |||||||
| STX | 3 | DISP | 6BXX | Store XR3 in CSL at EA (I+DISP) | |||||||
| STX | L | ADDR | 6C00XXXX | Store I in CSL at EA (Addr) | |||||||
| STX | L | 1 | ADDR | 6D00XXXX | Store XR1 in CSL at EA (Addr) | ||||||
| STX | L | 2 | ADDR | 6E00XXXX | Store XR2 in CSL at EA (Addr) | ||||||
| STX | L | 3 | ADDR | 6F00XXXX | Store XR3 in CSL at EA (Addr) | ||||||
| STX | I | ADDR | 6C80XXXX | Store I in CSL at EA (V in CSL at Addr) | |||||||
| STX | I | 1 | ADDR | 6D80XXXX | Store XR1 in CSL at EA (V in CSL at Addr) | ||||||
| STX | I | 2 | ADDR | 6E80XXXX | Store XR2 in CSL at EA (V in CSL at Addr) | ||||||
| STX | I | 3 | ADDR | 6F80XXXX | Store XR3 in CSL at EA (V in CSL at Addr) | ||||||
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